Nios® V Embedded Processor Design Handbook

ID 726952
Date 12/04/2023
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Document Table of Contents
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2.1.3. Specifying Base Addresses and Interrupt Request Priorities

To specify how the components added in the design interact to form a system, you need to assign base addresses for each agent component and assign interrupt request (IRQ) priorities for the JTAG UART and the interval timer. The Platform Designer provides a command - Assign Base Addresses - which automatically assigns proper base addresses to all components in a system. However, you can adjust the base addresses based on your needs.

The following are some guidelines for assigning base addresses:

  • Nios® V processor core has a 32-bit address span. To access agent components, their base address must range between 0x00000000 and 0xFFFFFFFF.
  • Nios® V programs use symbolic constants to refer to addresses. You do not have to choose address values that are easy to remember.
  • Address values that differentiate components with only a one-bit address difference produce more efficient hardware. You do not have to compact all base addresses into the smallest possible address range because compacting can create less efficient hardware.
  • Platform Designer does not attempt to align separate memory components in a contiguous memory range. For example, if you want multiple On-Chip Memory components addressable as one contiguous memory range, you must explicitly assign base addresses.

The Platform Designer also provides automation command - Assign Interrupt Numbers which connects IRQ signals to produce valid hardware results. However, assigning IRQs effectively requires an understanding to the overall software respond behavior.The Platform Designer cannot make educated guesses about the best IRQ assignment.

To interpret the IRQ priority, the lowest IRQ value has the highest priority. In an ideal system, the timer component must have the highest IRQ priority to maintain the accuracy of the system clock tick.