188.8.131.52. Hardware Design Flow
The following sections describe a step-by-step method for building a bootable system for a Nios® V processor application from OCRAM. The example below is built using Intel Arria 10 SoC development kit.
IP Component Settings
- Create your Nios® V processor project using Intel® Quartus® Prime and Platform Designer.
- Ensure the On-Chip Memory (RAM or ROM) Intel FPGA is added into your Platform Designer system.
- Enable Initialize memory content and Enable non-default initialization file with ram.hex in the on-chip memory.
Reset and Exception Agent Settings for Nios® V Processor
- In the Nios® V processor parameter editor, set the Reset Agent to OCRAM and Exception Agent to OCRAM.
Figure 73. Nios V Processor Parameter Editor Settings
- Click Generate HDL, the Generation dialog box appears.
- Specify output file generation options and then click Generate.
Intel® Quartus® Prime Settings
- In the Intel Quartus Prime software, click Assignment ➤ Device ➤ Device and Pin Options ➤ Configuration.
- Set Configuration scheme according to your FPGA configuration scheme
- Click OK to exit the Device and Pin Options window.
- Click OK to exit the Device window.
- Click Start Compilation to compile your project.
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