Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

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3.4. Clocks and Resets

Understanding how the Nios® V processor system clocking and reset domain interact with every peripheral it connects to is important. A simple Nios® V processor system starts with a single clock domain, and it can get complicated with a multi-clock domain system when a fast clock domain collides with a slow clock domain. You need to take note and understand how these different domains sequence out of reset and make sure there aren't any subtle problems.

For best practice, Intel recommends placing the Nios® V processor and boot memory in the same clock domain. Do not release the Nios® V processor from reset in a fast clock domain when it boots from a memory that resides in a very slow clock domain, which may cause an instruction fetch error. You may require some manual sequencing beyond what Platform Designer provides by default, and plan out reset release topology accordingly based on your use case. If you want to reset your system after it comes up and runs for a while, apply the same considerations to system reset sequencing and post reset initialization requirement.