Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project

After generating the Nios® V system design in Platform Designer, perform the following tasks to integrate the Nios® V system module into the Intel® Quartus® Prime FPGA design project.

  • Instantiate the Nios® V system module in the Intel® Quartus® Prime project
  • Connect signals from Nios® V system module to other signals in the FPGA logic
  • Assign physical pins location
  • Constrain the FPGA design

Did you find the information on this page useful?

Characters remaining:

Feedback Message