1. About this Document 2. Introduction 3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer 4. Nios® V Processor Software System Design 5. Nios® V Processor Configuration and Booting Solutions 6. Nios® V Processor - Using the MicroC/TCP-IP Stack 7. Nios® V Processor Debugging, Verifying, and Simulating 8. Document Revision History for the Nios® V Embedded Processor Design Handbook
5.1. Introduction 5.2. Linking Applications 5.3. Nios® V Processor Booting Methods 5.4. Introduction to Nios® V Processor Booting Methods 5.5. Nios® V Processor Booting from Configuration QSPI Flash 5.6. Nios V Processor Booting from On-Chip Memory (OCRAM) 5.7. Summary of Nios V Processor Vector Configuration and BSP Settings
7.4.1. Prerequisites 7.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer 7.4.3. Creating Nios V Processor Software 7.4.4. Generating Memory Initialization File 7.4.5. Generating System Simulation Files 7.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer
184.108.40.206. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader)
7. Nios® V Processor Debugging, Verifying, and Simulating
This chapter introduces the best practices for debugging the Nios V processor and verification for embedded design and simulation. Debugging and verifying an embedded system involves hardware and software components. To successfully debug an embedded system requires expertise in both hardware and software. This chapter helps you understand several tools and techniques that are useful in debugging, verifying, and bring up the embedded system.
Did you find the information on this page useful?