Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

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Document Table of Contents Generating the Nios® V/m Processor Example Design in Platform Designer

To generate the Nios® V/m processor in Platform Designer, perform the following steps:
  1. In the Intel® Quartus® Prime software, go to Tools Platform Designer.
  2. In the Platform Designer, select IP Variant.
  3. For Quartus project, select None.
  4. In the IP Variant dialog box, specify any name for your IP.
    Note: You do not need to save the IP later.
  5. Click Select in the Component type.
    1. The IP Catalog opens.
    2. Search for Nios V/m Processor Intel FPGA IP.
    3. Create the IP design.
  6. Click Example Design : "Hello World Example Design" and select your project folder. The .zip file is copied after you select the project folder.
    Figure 2. IP Parameter Editor for Nios® V/m Processor Intel® FPGA IP
  7. Close the IP Parameter Editor. When prompted with Save changes?. Click Don’t Save.
  8. Unzip the example design to your project folder. Refer to the following table for the example design files and the description.
Table 3.  Example Design File Description
File Description
software/app Folder containing source code for software application.
create_qsys.tcl TCL script to generate the example design .qsys file.
readme.txt Description and steps to build the example design.
toggle_issp.tcl TCL script to reset the design via In-System Sources and Probes (ISSP).
top.qpf Example design Quartus Project File (.qpf.) file.
top.qsf Example design Quartus Setting File (.qsf) file.
top.sdc Example design Synopsys* Design Constraints (.sdc) file.
top.v Top-level Verilog design.

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