Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

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3.3.3. On-Chip Memory Configuration – RAM/ROM

You can configure Intel FPGA On-Chip Memory IPs as RAM or ROM.

RAM provides read and write capability and has a volatile nature. If a Nios V processor is booting from an on-chip RAM, you must make sure boot content is preserved and not corrupted in the event of a reset during run time.

If a Nios V processor is booting from ROM, any software bug on the Nios V processor cannot erroneously overwrite the contents of On-Chip Memory. Thus, reducing the risk of boot software corruption. Alternatively, you can enable the On-Chip Memory Enable Debug Access Port feature, allowing you to write to On-Chip ROM.

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