Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

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Document Table of Contents Generating the Nios® V/m Processor Example Design System in Platform Designer

To generate the Nios® V/m processor example design system in Platform Designer, perform the following steps:
  1. Open the project, go to Tool > Platform Designer.
  2. Create a new Platform Designer system and name it as sys.qsys.
  3. Save the system.
  4. In the Platform Designer, go to View > System Scripting. The System Scripting window appears.
  5. Under the Project Scripts, add and click Run Script to run the create_qsys.tcl.
    Figure 3. System Scripting window
  6. The generated Platform Designer system consist of a clock bridge, reset bridge, Nios® V/m processor, on-chip memory and JTAG UART IP.
  7. Click Generate HDL to generate the system HDL.
    Note: To target another Intel FPGA device other than the Arria 10 SoC Development Kit, update the FAMILY, DEVICE, and clock pin assignments in the top.qsf file.
  8. Click Processing > Start Compilation to perform a full hardware compilation and generate the .sof file.

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