Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

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Document Table of Contents

6.4.3. Acquiring the Example Design Files

Generating the µC/TCP-IP Example Designs

To generate the µC/TCP-IP Example Designs using Platform Designer, perform the following steps:

  1. In the Intel® Quartus® Prime software, go to Tools > Platform Designer.
  2. In the Platform Designer, select IP Variant.
  3. For Quartus project, select None.
  4. In the IP Variant dialog box, specify any name for your IP.
    Note: You do not need to save the IP later.
  5. Click Select in the Component type.
    1. The IP Catalog opens.
    2. Search for Nios V/m Processor Intel FPGA IP.
    3. Create the IP design.
    Figure 80. IP Parameter Editor for Nios® V/m Processor Intel FPGA IP
  6. Click one of the available example designs and select your project folder. In this chapter, the associated example designs are:
    1. Example Design: “µC/TCP-IP IPerf Example Design"
    2. Example Design: “µC/TCP-IP Simple Socket Server Example Design"
  7. Close the IP Parameter Editor. When prompted with Save changes ?, click Don’t Save.
  8. Unzip the example design to your project folder. Refer to the following table for the example design files and the description.

To generate the Example Design using CLI, use the following command:

<Intel Quartus Prime installation directory>/niosv/bin/niosv-shell
ip-deploy --component-name=intel_niosv_m --output-name=niosv_m.ip
qsys-generate niosv_m.ip \
    --example_design=<niosv_m.uc_tcp_ip_iperf_example_design or 
unzip < or
Table 14.  Example Design Files Description
File Description
scripts Folder containing scripts to generate and build the example design.
sdc Folder containing the Synopsys Design Constraint (.sdc) files for the example design.
software Folder containing source code for the µC/TCP-IP application using Nios® V processor. Python script to build the example design. Description and steps to build the example design. Python script to program the .sof file, and run the system.
toggle_issp.tcl TCL script to reset the design via In-System Sources and Probes (ISSP).
top.v Top-level Verilog design. Python script to update the example design after editing the software design files.

Running the µC/TCP-IP Example Designs

The µC/TCP-IP Example Designs are provided with scripts to facilitate the build flow. The scripts are stored in the scripts folder. You may refer to the readme file ( to develop the example designs using the provided scripts, or develop the design manually using the Nios V tools.

The steps are as followed:

  1. Setup the PATH variables (Refer to Setting Up Open-Source Tools).
  2. Launch the Nios V Command Shell.
  3. Run to build the example design.
  4. Run if any changes are made to the software design files. The script has some options. See for more details.
  5. Run to program the .sof file into an Intel FPGA board and run the µC/TCP-IP example design.

For more information about the hardware and software development follow, refer to Hardware Development Flow and Software Development Flow.

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