Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5. Nios® V Processor Configuration and Booting Solutions

This chapter describes the various boot or software execution options available with the Nios® V processor. You can configure the Nios® V processor to boot and execute software from different memory locations. The boot memory is the Quad Serial Peripheral Interface (QSPI) flash or On-Chip Memory (OCRAM).