Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

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5.4.3. Nios® V Processor Application Execute-In-Place from OCRAM

In this method, the Nios® V processor reset address is set to the base address of the on-chip memory (OCRAM). The application binary (.hex) file is loaded into the OCRAM when the FPGA is configured, after the hardware design is compiled in the Intel® Quartus® Prime software. Once the Nios® V processor resets, the application begins executing and branches to the entry point.
  • Execute-In-Place from OCRAM does not require boot copier because Nios® V processor application is already in place at system reset.
  • Intel recommends enabling alt_load() for this booting method so that the embedded software behaves identically when reset without reconfiguring the FPGA device image.

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