1. About this Document 2. Introduction 3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer 4. Nios® V Processor Software System Design 5. Nios® V Processor Configuration and Booting Solutions 6. Nios® V Processor - Using the MicroC/TCP-IP Stack 7. Nios® V Processor Debugging, Verifying, and Simulating 8. Document Revision History for the Nios® V Embedded Processor Design Handbook
5.1. Introduction 5.2. Linking Applications 5.3. Nios® V Processor Booting Methods 5.4. Introduction to Nios® V Processor Booting Methods 5.5. Nios® V Processor Booting from Configuration QSPI Flash 5.6. Nios V Processor Booting from On-Chip Memory (OCRAM) 5.7. Summary of Nios V Processor Vector Configuration and BSP Settings
7.4.1. Prerequisites 7.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer 7.4.3. Creating Nios V Processor Software 7.4.4. Generating Memory Initialization File 7.4.5. Generating System Simulation Files 7.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer
220.127.116.11. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader)
5.4.3. Nios® V Processor Application Execute-In-Place from OCRAM
In this method, the Nios® V processor reset address is set to the base address of the on-chip memory (OCRAM). The application binary (.hex) file is loaded into the OCRAM when the FPGA is configured, after the hardware design is compiled in the Intel® Quartus® Prime software. Once the Nios® V processor resets, the application begins executing and branches to the entry point.
- Execute-In-Place from OCRAM does not require boot copier because Nios® V processor application is already in place at system reset.
- Intel recommends enabling alt_load() for this booting method so that the embedded software behaves identically when reset without reconfiguring the FPGA device image.
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