Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

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5.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash

Intel designed the Generic Serial Flash Interface Intel FPGA IP so that the boot flash address space is immediately accessible to the Nios® V processor upon system reset, without the need to initialize the memory controller or memory devices. This enables the Nios® V processor to execute application code stored on the boot devices directly without using a boot copier to copy the code to another memory type.

When the Nios® V processor application execute-in-place from boot flash, the BSP Editor performs the following functions:
  • Sets the .text linker sections to the boot flash memory region.
  • Sets the .bss,.rodata, .rwdata, .stack and .heap linker sections to the RAM memory region.
You can enable the alt_load() function in the BSP Settings to copy the data sections (.rodata, .rwdata,, .exceptions) to the RAM upon system reset. The code section (.text) remains in the boot flash memory region.

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