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1. About this Document
2. Introduction
3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer
4. Nios® V Processor Software System Design
5. Nios® V Processor Configuration and Booting Solutions
6. Nios® V Processor - Using the MicroC/TCP-IP Stack
7. Nios® V Processor Debugging, Verifying, and Simulating
8. Document Revision History for the Nios® V Embedded Processor Design Handbook
5.1. Introduction
5.2. Linking Applications
5.3. Nios® V Processor Booting Methods
5.4. Introduction to Nios® V Processor Booting Methods
5.5. Nios® V Processor Booting from Configuration QSPI Flash
5.6. Nios V Processor Booting from On-Chip Memory (OCRAM)
5.7. Summary of Nios V Processor Vector Configuration and BSP Settings
7.4.1. Prerequisites
7.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer
7.4.3. Creating Nios V Processor Software
7.4.4. Generating Memory Initialization File
7.4.5. Generating System Simulation Files
7.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
2.3.1.1. Hardware and Software Requirements
Intel uses the following hardware and software to build a Nios® V/m processor system:
- Supported Intel FPGA devices:
- Intel® Cyclone® 10 GX
- Intel® Arria® 10
- Intel® Stratix® 10
- Intel® Agilex™
- Intel® Quartus® Prime Pro Edition software version 21.3 or later
- Currently supported open-source tools:
- GNU RISC-V Embedded GCC (v10.2.0-1.2 or later)
- CMake (v3.14.10 or later)
- xPack Windows Build Tools (v3.2.1.1 or later)
- Eclipse* CDT for Embedded C/C++ Developers
Note:
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You need to acquire the license for the Nios® V processor to compile the design in Intel® Quartus® Prime software.
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Intel® Quartus® Prime Software does not includes the open-source tools. Please refer to Setting Up Open-Source Tools for the installation details.
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