Nios® V Embedded Processor Design Handbook

ID 726952
Date 4/04/2022

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2.3.2. Nios® V/m Processor Example Design

This section provides the design flow to generate and build a Nios® V/m processor example design system.

The example design provided is a “Hello World” program. The complete system is build using the IP blocks in the following table and shown in the following figure:

Table 2.  Example Design Component Description
Components Description
Nios® V/m Processor Intel® FPGA IP Runs application by executing instructions.
JTAG UART Intel® FPGA IP Enables serial character communication between Nios® V/m processor and host computer.
On-Chip Memory Intel® FPGA IP Stores data and instructions.
Figure 1.  Nios® V/m Example Design Block Diagram

Before building and running an application on Nios® V/m processor, you must compile and configure the correct hardware design on the FPGA. The example design provided was configured to run on the Intel Arria® 10 SoC Development Kit.

Note: You can modify the provided design to target your desired board by configuring the target device setting in the provided top.qsf and create_qsys.tcl file, and clock pin setting in the top.qsf file. For more information, refer to Generating the Nios V/m Processor Example Design System in Platform Designer.

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