2.3.2. Nios® V/m Processor Example Design
This section provides the design flow to generate and build a Nios® V/m processor example design system.
The example design provided is a “Hello World” program. The complete system is build using the IP blocks in the following table and shown in the following figure:
|Nios® V/m Processor Intel® FPGA IP||Runs application by executing instructions.|
|JTAG UART Intel® FPGA IP||Enables serial character communication between Nios® V/m processor and host computer.|
|On-Chip Memory Intel® FPGA IP||Stores data and instructions.|
Before building and running an application on Nios® V/m processor, you must compile and configure the correct hardware design on the FPGA. The example design provided was configured to run on the Intel Arria® 10 SoC Development Kit.
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