AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

Drive-On-Chip Reference Design Features

  • Multiple field-oriented control (FOC) loop implementations:
    • Fixed- or floating-point implementation targeting the ARM Cortex A9 processor on SoC devices
    • Fixed- or floating-point implementation with Nios II processors targeting MAX 10 FPGA devices
    • Fixed and floating-point accelerator implementations designed using Simulink model-based design flow with DSP Builder
  • Integration in a single FPGA of single and multiaxis motor control IP including:
    • PWM for two-level IGBT
    • Sigma delta ADC interfaces for motor current feedback and DC link voltage measurement
    • Position feedback with EnDat or BiSS
  • Vibration suppression (SoC devices only):
    • DSP Builder-designed FFT accelerator
    • Peak detection
    • Suppression filter
  • System Console GUI for motor feedback information, vibration suppression demonstration, and control of motors

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