Visible to Intel only — GUID: hco1433528070873
Ixiasoft
Visible to Intel only — GUID: hco1433528070873
Ixiasoft
ADC Interface
To offset the effect of current ripple, the reference design centers the ADC reading at the PWM reversal point. The reference design configures the start pulse to be at:
(settling time)/2
The reference design configures the phase current ADC interfaces to a decimation rate of M = 128, which requires a settling time of 19.2 s. To centre the ADC sampling, apply an offset to the PWM trigger of 9.6 s (480 clock periods @ 50 MHz).
For an ADC clock rate of 20 MHz,
Decimation Rate | PWM Trigger Down | PWM Trigger Up | Offset (s) |
---|---|---|---|
64 | 240 | PWMMAX –240 | 4.8 |
128 | 480 | PWMMAX – 480 | 9.6 |
An additional ADC measures the combined current flowing from the DC link for power consumption measurements.