AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

ADC Interface

The reference design uses a start pulse, which the PWM generates, on the ADC input to start the ADC interface. If you need to start multiple ADC interfaces from the same start pulse, use a conduit splitter component.

To offset the effect of current ripple, the reference design centers the ADC reading at the PWM reversal point. The reference design configures the start pulse to be at:

(settling time)/2

Figure 16. ADC Start Pulse and Settling Time

The reference design configures the phase current ADC interfaces to a decimation rate of M = 128, which requires a settling time of 19.2 s. To centre the ADC sampling, apply an offset to the PWM trigger of 9.6 s (480 clock periods @ 50 MHz).

Note: If you change to decimation rate M = 64, you must also adjust the PWM trigger parameters in the PWM to correctly centre the ADC sampling.

For an ADC clock rate of 20 MHz,

Table 14.  ADC Interface Offsets for M= 64 and 128
Decimation Rate PWM Trigger Down PWM Trigger Up Offset (s)
64 240 PWMMAX –240 4.8
128 480 PWMMAX – 480 9.6

An additional ADC measures the combined current flowing from the DC link for power consumption measurements.

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