AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

6-Channel PWM

The 6-channel PWM provides an 8-kHz switching period, and a start pulse every 16 kHz shortly before the reversal point of the PWM counter. This pulse goes to the ADC to start capturing data and when the ADC finishes it sends an interrupt to the processor. The interrupt output from the first axis and drive0 (doc_adc_irq) is connected to the processor. You may leave the interrupt outputs from the other axes unconnected.

The PWM provides synchronization between multiple PWM instances. To implement this feature the reference design programs the PWMs identically: in Qsys one instance is the master PWM and connects the sync_out port to the other PWM sync_in port. For additional instances, continue chaining the sync_out port from the last instance to the next sync_in port. For example:

sync_out (PWM0) to sync_in (PWM1) and sync_out(PWM1) to sync_in(PWM2)

An internal counter defines the PWM period from 0 to PWMMAX and then back to 0. The design configures it for an 8-kHz rate, and the internal clock rate of the PWM is 50 MHz. To achieve an 8-kHz period with an internal clock rate of 50 MHz, set the carrier register value to 3,125. Therefore:

carrier = (50 MHz / 8 kHz) / 2 = 3,125

Figure 15. PWM Counter Value

The carrier_latch output indicates to the position encoder to take a position reading. It is high for one clock cycle when the counter is at zero and at PWMMAX.

The start output indicates to the phase current ADC interfaces to start sampling. It is offset from the carrier_latch position, so it occurs at a fixed position before it. The pwm_trigger_up sets the trigger value when the PWM counter is counting up; pwm_trigger_down sets the trigger value when counting down (Table 14).

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