Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 9/26/2022
Public
Document Table of Contents

4.5.3.2. Receive User Data Interface Examples

The Interlaken Look-aside mode only supports packet mode data transfer. The following example illustrate how to use Interlaken Look-aside RX user data interface during a normal packet transfer:

Packet Mode Transfer Example

This example illustrates the expected behavior of the Interlaken Look-aside application interface receive signals during a packet transfer in packet mode.
Figure 25. Packet Transfer on Receive InterfaceThe following figure illustrates two packet transfer of 120 bytes and 49 bytes on the transmit interface with number of lanes is equal to eight and TX_CREDIT_LATENCY is equal to four.
From cycle 0 to cycle 4, there is no valid data drop by the IP as irx_valid deassert.

In cycle 5, the IP core asserts irx_valid, and all of irx_idle bits indicating that irx_dout_words carry idle control words.

In cycle 6, the IP deasserts irx_valid signal again indicating all of other signals are invalid.

In cycle 7, the IP core asserts irx_valid with irx_idle[7:0] is equal to 8'h0, which indicates irx_sop, irx_eopbits, and irx_dout_words carry valid data. The assertion of itx_sop[7] indicates the start of packet at the leftmost words. Corresponding irx_chan[7] indicates the channel associated with this data packet following this control word. With irx_eopbits is 0x0, irx_dout_words represents the actual data words of packet.

In cycle 8, the assertion of irx_eopbits[3] terminates the transfer of data, which happens on the rightmost words. All data words on irx_dout_words[511:0] are the last words of the packet. irx_eopbits[3:0]== 4'b1000 indicates all 8 bytes of the rightmost data word are valid.

In cycle 9, IP core deasserts irx_valid signal again indicating that all of the other signals are not valid.

In cycle 10, IP core flushes new packet with assertion of irx_sop[7] and irx_valid. The packet terminated in the same cycle as well with assertion of irx_eopbits[3]. The rx_eopbits[3:0]== 4’b1001 indicates only 1 byte of the rightmost words is valid. In this cycle, IP core outputs 49 bytes of data which is accessible from irx_dout_words[447:56].

In cycle 11, IP core deasserts irx_valid signal again indicating that all of other signals are not valid.

In cycle 12, IP core asserts irx_valid and all of irx_idle bits indicating that irx_dout_words carry idle control words.

This signal behavior correctly transfers first data packet as follows:
  • In cycle 7, the IP core outputs burst control word and 56 bytes of valid data (data 1).
  • In cycle 8, the IP core output 64 bytes of valid data (data 2).

The total packet length for the first packet is 56+64= 120 bytes.

This signal behavior correctly transfers second data packet as follows:
  • In cycle 10, the IP core outputs burst control word and 49 bytes of valid data (data 3).

The total packet length for the first packet is 49 bytes.

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