DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

7.2. DisplayPort Intel® FPGA IP Sink Parameters

You set parameters for the sink using the DisplayPort Intel® FPGA IP parameter editor.

Table 59.  Sink Parameters

Parameter

Description

Device family

Select the targeted device family: Intel® Agilex™ , Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria V GX, Arria V GZ, Cyclone V, or Stratix V.

Support DisplayPort sink

Turn on to enable DisplayPort sink.

Maximum video output color depth

Determines the maximum video input color depth (bits per color) supported by the DisplayPort source. Select 6, 8, 10, 12 or 16 bpc. DisplayPort sink supports RGB, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0 video formats by default.

RX maximum link rate

Select the maximum link rate supported: 20 Gbps, 10 Gbps, 8.1 Gbps, 5.4 Gbps, 2.7 Gbps, or 1.62 Gbps.

Note: Cyclone V devices only support up to 2.7 Gbps. 8.10 Gbps is only available in quad symbols per clock for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ devices.
Note: 10 Gbps is only available on Intel® Stratix® 10 devices.

Maximum lane count

Select the maximum lanes supported: 1, 2, or 4.

Note: If you turn on the Support MST parameter, the maximum lane count is fixed to 4 lanes.

Symbol input mode

Determines the RX transceiver data width in symbols per clock. Select dual (20 bits) or quad (40 bits).

Dual symbol mode saves logic resource but requires the core to run at twice the clock frequency of quad symbol mode. If timing closure is a problem in the device, you should consider using quad symbol mode.

Note: For 8.1 Gbps and above, this option is limited to Quad (40 bits).

Pixel output mode

Select the number of pixels per clock (single, dual, or quad symbol).

  • If you select dual pixels per clock, the pixel clock is ½ of the full rate clock and the video port becomes two times wider.
  • If you select four pixels per clock, the pixel clock is ¼ of the full rate clock and the video port becomes four times wider.
Enable Active Video Data Protocols

Select the following options to configure the type of Video Interface:

  • None
  • AXIS-VVP Full
Note:

Sink scrambler seed value

Select the initial seed value for the scrambler block.

  • DP: 16’hFFFF
  • eDP: 16’hFFFE
Note: All DP2.0 link rates limit this to 16’hFFFF.

Export MSA

Turn on to enable the sink to export the MSA interface to the top-level port interface.

IEEE OUI

Specify an IEEE organizationally unique identifier (OUI) as part of the DPCD registers.

Enable GPU control

Turn on to use an embedded controller to control the sink.

Note: All DP2.0 link rates will require Enable GPU control to be set.

Enable AUX debug stream

Turn on to enable AUX traffic output to an Avalon-ST port.

Support CTS test automation

Turn on to support automated test features.

Support PRBS Checker

DP2.0 only. Supports PRBS* error checking during Link Quality Test Mode.

Support GTC

The Global Time Code (GTC) feature is not available. However, if you want to use this feature, contact your nearest Intel FPGA sales representative or file a Service Request.

Support secondary data channel

Turn on to enable secondary data.

Support audio data channel

Turn on to enable audio packet decoding.

Note: To use this parameter, you must also turn on Support secondary data channel.

Number of audio data channels

Select the number of audio channels (2 or 8).

Support MST

Turn on to enable multi-stream support.

You must turn on Enable GPU control to support MST mode.
Note: For multi-stream support, the maximum lane count is fixed to four lanes.
Note: In DP2.0, turn on to enable multiple streams support and set the max stream count accordingly.

Max stream count

Specify the maximum amount of streams supported: 2, 3, or 4.
Note: To use this parameter, you must turn on the Support MST parameter.

Support HDCP 1.3

Turn on to enable HDCP 1.3 RX support. This parameter can only be used when you specify these settings:

  • Maximum lane count: 4
  • Symbol input mode: Dual (20 bits) or Quad (40 bits)
  • Enable GPU control: On
Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html .

Support HDCP 2.3

Turn on to enable HDCP 2.3 RX support. This parameter can only be used when you specify these settings:

  • Maximum lane count: 4
  • Symbol input mode: Dual (20 bits) or Quad (40 bits)
  • Enable GPU control: On
Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html .
Support HDCP Key Management Turn on to enable HDCP key management support. To use this parameter, you must turn on the Support HDCP 1.3 or Support HDCP 2.3 parameters.
Note:
  1. The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html .
  2. The HDCP key management support from version 21.3 onwards is not compatible with the KEYENC version 21.2 and earlier. You need to re-encrypt the HDCP production keys using the KEYENC version 21.3 onwards. Refer to DisplayPort Intel Arria 10 FPGA IP Design Example User Guide and DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide for more details.