DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022

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Target Average Time Slots

Address: 0x00aa

Direction: RW

Reset: 0x40404040

Table 109.  DPTX_MST_TAVG_TS Bits


Bit Name


31 Unused  
30:24 TAVG_TS3

Target Average Time Slots for Stream 3

23 Unused  
22:16 TAVG_TS2

Target Average Time Slots for Stream 2

15 Unused  
14:8 TAVG_TS1

Target Average Time Slots for Stream 1

7 Unused  
6:0 TAVG_TS0

Target Average Time Slots for Stream 0

TAVG_TS x is expressed as the fractional part of the number of time slots per MTU occupied by Stream x times 64; assuming the allocated time slots are the ceiling of this number. For example, if 4.7 time slots/MTU are occupied (5 time slots/MTU are allocated in the VCP ID table.

TAVG_TS x = CEIL (FRAC (4.7)*64) = CEIL (0.7*64) = 45

The achieved precision for Target Average Time Slots regulation is 1/64 = 0.015625.

If TAVG_TS x is set to a value greater than 63, VCP fill is sent to each allocated time slot.