DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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10.2.16. DPTX0_VBID

Address: 0x002f

Direction: RO

Reset: 0x00000000

Table 80.  DPTX0_VBID Bits

Bit

Bit Name

Function

31:8

Unused

 

7

MSA_LOCK

0 = Input video timing unstable

1 = Input video timing stable

6:5

Unused  

4:0

VBID[4:0]

VB-ID flags (refer to the VESA DisplayPort Standard).