DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
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10.2.8. DPTX0_MSA_VSTART

Address: 0x0027

Direction: RO

Reset: 0x00000000

Note: This register is RO if TX_VIDEO_IM_ENABLE = 0 and RW if TX_VIDEO_IM_ENABLE = 1.
Table 72.  DPTX0_MSA_VSTART Bits

Bit

Bit Name

Function

31:16

Unused

15:0

VSTART

Main stream attribute VSTART