DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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4.3.4.2. Copy the Design Files to Your Working Directory

In this step, you copy the hardware demonstration files to your working directory.

Copy the files using the command:

cp -r <IP root directory>/ altera / altera_dp / hw_demo /<device_board> <working directory>

where <device_board> is av_sk_4k for Arria V GX starter kit, cv for Cyclone V GT development kit, sv for Stratix V development kit, mst_av for Arria V MST design, and mst_sv for Stratix V MST design.

You can also copy the design example through the DisplayPort Intel® FPGA IP parameter editor. Turn on Generate Example Design on the DisplayPort Intel® FPGA IP parameter editor before you generate your design. The software copies the SST design example files from altera/altera_dp/hw_demo/<device_board> to your working directory.
Note: The generated design example may not be aligned to your configured parameter settings.

Your working directory should contain the files shown in the following tables.

Table 17.  Hardware Demonstration Files for Arria V, Cyclone V, and Stratix V DevicesFiles are named with <prefix>_<name>.<extension> where <prefix> represents the device (av for Arria V devices, cv for Cyclone V devices, and sv for Stratix V devices).

File Type

File

Description

Verilog HDL design files

top.v

Top-level design file.

bitec_reconfig_alt_ <prefix> .v

Reconfiguration manager top-level. This module is a high-level FSM that generates the control signals to reconfigure the VOD and pre-emphasis, selects the PLL reference clock, and reconfigures the clock divider setting. The FSM loops through all the channels and transceiver settings.

altera_pll_reconfig_core.v

altera_pll_reconfig_mif_reader.v

altera_pll_reconfig_top.v

bitec_cc_fifo.v

bitec_cc_pulse.v

bitec_clkrec.v

bitec_fpll_cntrl.v

bitec_fpll_reconf.v

bitec_loop_cntrl.v

bitec_vsyncgen.v

clkrec_pll_ <prefix> .v

Clock recovery core encrypted design files.

IP Catalog files

video_pll <prefix> .v

pll_135.v

gxb_reconfig.v

gxb_reset.v

gxb_rx.v

gxb_tx.v

IP Catalog variants for the various helper IP cores.

Platform Designer system

control.qsys

Platform Designer system file.

Intel® Quartus® Prime IP files

bitec_reconfig_alt_ <prefix> .qip

bitec_clkrec_dist.qip

bitec_clkrec.qip

Intel® Quartus® Prime IP files that list the required submodule files.

Scripts

runall.tcl

Script to set up the project, generate the IP and Platform Designer system, and compile.

assignments.tcl

Top-level TCL file to create the project assignments.

build_ip.tcl

TCL file to build the DisplayPort example design IP blocks.

build_sw.sh

Script to compile the software.

Miscellaneous

example.sdc

Top-level SDC file.

bitec_clkrec.sdc

Clock recovery core SDC file.

Software files (in the software directory)

dp_demo_src\

Directory containing the example application source code.

btc_dprx_syslib\

System library for the RX API.

btc_dptx_syslib\

System library for the TX API.