DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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10.1.1. DPTX_TX_CONTROL

The IRQ is asserted when AUX_IRQ_EN = 1 and in register DPTX_AUX_CONTROL flag MSG_READY = 1. IRQ is de-asserted by setting AUX_IRQ_EN to 0 or reading from DPTX_AUX_COMMAND. IRQ is also asserted if HPD_IRQ_EN = 1 and a new HPD event is detected (HPD_EVENT in register DPTX_TX_STATUS different from 00). IRQ is de-asserted by setting HPD_IRQ_EN to 0 or reading from DPTX_TX_STATUS.

Setting LANE_COUNT to 00000 causes the transmitter to always send a logical zero (i.e., a constant voltage level). This function can be used as a surrogate for “power down” for link layer compliance testing.

Field TX_LINK_RATE drives the respective tx_reconfig port.

Address: 0x0000

Direction: RW

Reset: 0x00000000

Table 62.  DPTX_TX_CONTROL Bits

Bit

Bit Name

Function

31

HPD_IRQ_EN

Enables an IRQ issued to the Nios® II processor on an HPD event:

  • 0 = disable
  • 1 = enable

30

AUX_IRQ_EN

Enables an IRQ issued to the Nios® II processor when an AUX channel transaction reply is received from the sink:

  • 0 = disable
  • 1 = enable

29

Unused

N/A

28:21

TX_LINK_RATE

Main link rate:

  • 0x06 = 1.62 Gbps
  • 0x0a = 2.7 Gbps
  • 0x14 = 5.4 Gbps
  • 0x1e = 8.1 Gbps
  • 0x01 = 10 Gbps
  • 0x02 = 20 Gbps

20

Reserved

Reserved

19 ENHANCED_FRAME

0 = Standard framing

1 = Enhanced framing

18 Reserved Reserved
17 PRECODING_DISABLE

128B/132B Channel Coding only. Disables Precoding

0 = Precoding enabled

1 = Precoding disabled

16:12 Reserved Reserved
11:10 CHANNEL_CODING_SET

0x1 = 8B/10B Channel Coding

0x2 = 128B/132B Channel Coding

9:5

LANE_COUNT

Lane count:

  • 00000 = Reserved
  • 00001 = 1
  • 00010 = 2
  • 00100 = 4

4:0

TP

Current training pattern.

8B/10B Channel Coding:

  • 0_0000 = Normal video
  • 0_0001 = Training pattern 1 (D10.2)
  • 0_0010 = Training pattern 2
  • 0_0011 = Training pattern 3
  • 0_0111 = Training pattern 4
  • 0_0100 = Video idle pattern
  • 0_1001 = D10.2 test pattern (same as training pattern 1)
  • 0_1010 = Symbol error rate measurement pattern
  • 0_1011 = PRBS7
  • 0_1100 = 80-bit custom pattern
  • 0_1101 = CP2520 test pattern 1 (HBR2 compliance test pattern)
  • 0_1111 = CP2520 test pattern 3 (same as training pattern 4)

128B/132B Channel Coding:

  • 1_0000 = Normal video
  • 1_0001 = Training pattern 1
  • 1_0010 = Training pattern 2
  • 1_0101 = 128b/132b_TPS1 test pattern
  • 1_0110 = 128b/132b_TPS2 test pattern
  • 0_0111 = PRBS7
  • 0_1000= PRBS9
  • 0_1001 = PRBS11
  • 0_1010 = PRBS15
  • 0_1011 = PRBS23
  • 0_1100 = PRBS31
  • 0_1101 = 264-bit custom pattern
  • 0_1110 = SQnum pattern