DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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6.1. Transceiver to IP Parallel Data Interface Width

Figure 30. DisplayPort 2.0 Sink High Level Block Diagram

DP 8B/10B Channel Coding has a native symbol size of 10-bits. This value multiplied by the SYMBOLS_PER_CLOCK parameter determines the size of the IP parallel data interface from the Transceiver (XCVR). Therefore, the DP1.4 datapath in the IP, configured with QUAD SYMBOLS_PER_CLOCK, has a 40-bit wide parallel data interface from the transceiver.

DP 128B/132B Channel Coding has a native 32- or 64-bit symbol size, which is multiplied by 2 depending on link rates. Therefore, the DP2.0 datapath in the IP has a 32/64-bit wide parallel data interface from the transceiver.

Given that DP2.0 is backward compatible with DP1.4 and that selecting UHBR10 link rates requires all link rates below that to be supported (RBR, HBR, HBR2, HBR3), the external IP interface is maintained at 40-bit wide, while internally the IP muxes the input between the 40-bit wide DP1.4 datapath and 32/64-bit wide DP2.0 datapath.

Figure 31. DisplayPort 2.0 Sink Functional Block Diagram
The DP2.0 RX datapath consists of two stages, the Logical PHY (LPHY) and the Link Layer (LL). During Link Training, the LPHY will first obtain symbol lock and interlace alignment. Once the Link Training is completed, the LPHY performs 128B/132B decoding, consisting of:
  1. FEC decoding where symbol errors are detected and corrected.
  2. Descrambling.
  3. Intra_Lane Super Shifting Deshifting to reverse the Super Symbol Shifting done on the transmit side.
  4. Lane Converter to convert from 1 or 2 physical lanes to fixed 4 logical lanes.
The 128B/132B decoded symbols are then sent to the LL where:
  1. LLCP demuxer locks onto the LLCP marker sequence.
  2. MTP demuxer where streams symbols are extracted accroding to the VC Payload table.
  3. LL decoder (one per-stream) where the stream symbols are decoded into:
    • Video stream
    • LPCM Audio stream
    • Secondary data stream

You configure the sink to output the video data as a proprietary data stream. You specify the output pixel data width at 6, 8, 10, 12, or 16 bpc. This format can interface with downstream Video and Image Processing (VIP) Suite components.

The AUX controller can operate in an autonomous mode in which the sink controls all AUX channel activity without an external embedded controller. The IP outputs an AUX debugging stream so that you can inspect the activity on the AUX channel in real time.