DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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Document Table of Contents

7.1. DisplayPort Intel® FPGA IP Source Parameters

You set parameters for the source using the DisplayPort Intel® FPGA IP parameter editor.

Table 58.  Source Parameters

Parameter

Description

Device family

Select the targeted device family: Intel® Agilex™ , Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria V GX, Arria V GZ, Cyclone V, or Stratix V.

Support DisplayPort source

Turn on to enable DisplayPort source.

Maximum video input color depth

Determines the maximum video input color depth (bits per color) supported by the DisplayPort source. Select 6, 8, 10, 12 or 16 bpc.

Note: DisplayPort source supports RGB, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0 video formats by default.

TX maximum link rate

Select the maximum link rate supported: 20 Gbps, 10 Gbps, 8.1 Gbps, 5.4 Gbps, 2.7 Gbps, or 1.62 Gbps.

Note: Cyclone V devices only support up to 2.7 Gbps. 8.10 Gbps is only available in quad symbols per clock for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ devices.
Note: 10 Gbps is only available on Intel® Stratix® 10 devices.

Maximum lane count

Select the maximum lanes supported: 1, 2, or 4.

Note: If you turn on the Support MST parameter, the maximum lane count is fixed to 4 lanes.

Symbol output mode

Determines the TX transceiver data width in symbols per clock. Select dual (20 bits) or quad (40 bits).

Dual symbol mode saves logic resource but requires the core to run at twice the clock frequency of quad symbol mode. If timing closure is a problem in the device, you should consider using quad symbol mode.

Note: For 8.1 Gbps and above, this option is limited to Quad (40 bits).

Pixel input mode

Select the number of pixels per clock (single, dual, or quad symbol).

  • If you select dual pixels per clock, the pixel clock is ½ of the full rate clock and the video port becomes two times wider.
  • If you select four pixels per clock, the pixel clock is ¼ of the full rate clock and the video port becomes four times wider.

Scrambler seed value

Select the initial seed value for the scrambler block.

  • DP: 16’hFFFF
  • eDP: 16’hFFFE
Note: All DP2.0 link rates limit this to 16’hFFFF.
Enable Active Video Data Protocols

Select the following options to configure the type of Video Interface:

  • None
  • AXIS-VVP Full
Note:

Enable Video input Image port

Turn on to enable the video image interface. Turn off to use the traditional HSYNC/VSYNC/DE video input interface.
Note: You can only configure this parameter when Enable Active Video Data Protocols = “None”. (Refer to Section Video Interface (TX Video IM Enable = 0) and Video Interface (TX Video IM Enable = 1)).

Support analog reconfiguration

Turn on to reconfigure VOD and pre-emphasis values.

Enable AUX debug stream

Turn on to send source AUX traffic output to an Avalon-ST port.

Support CTS test automation

Turn on to support CTS test automation.

Support GTC

The Global Time Code (GTC) feature is not available. However, if you want to use this feature, contact your nearest Intel FPGA sales representative or file a Service Request.

Support secondary data channel

Turn on to enable secondary data.

Support audio data channel

Turn on to enable audio packet encoding.

Note: To use this parameter, you must turn on the Support secondary data channel parameter.

Number of audio data channels

Select the number of audio channels (2 or 8).

Support MST

Turn on to enable multi-stream support.
Note: For multi-stream support, the maximum lane count is fixed to four lanes.
Note:

In DP2.0, turn on to enable multiple stream support and set the max stream count accordingly.

Max stream count

Specify the maximum amount of streams supported: 2, 3, or 4.

Note: To use this parameter, you must turn on the Support MST parameter.

Support HDCP 1.3

Turn on to enable HDCP 1.3 TX support. This parameter can only be used when you specify these settings:

  • Maximum lane count: 4
  • Symbol output mode: Dual (20 bits) or Quad (40 bits)
Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html .

Support HDCP 2.3

Turn on to enable HDCP 2.3 TX support. This parameter can only be used when you specify these settings:

  • Maximum lane count: 4
  • Symbol output mode: Dual (20 bits) or Quad (40 bits)
Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html .
Support HDCP Key Management Turn on to enable HDCP key management support. To use this parameter, you must turn on the Support HDCP 1.3 or Support HDCP 2.3 parameters.
Note:
  1. The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html .
  2. The HDCP key management support from version 21.3 onwards is not compatible with the KEYENC version 21.2 and earlier. You need to re-encrypt the HDCP production keys using the KEYENC version 21.3 onwards. Refer to DisplayPort Intel Arria 10 FPGA IP Design Example User Guide and DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide for more details.