6.6.6. Clocked Video Input Interface

DisplayPort Intel® FPGA IP User Guide

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Date 9/02/2022

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6.6.6. Clocked Video Input Interface

The rxN_video_out interface may interface with a clocked video input (CVI). CVI accepts the following video signals with a separate synchronization mode: datavalid, de, h_sync, v_sync, f, locked, and data.

The DisplayPort rxN_video_out interface has the following signals: rxN_vid_valid, rxN_vid_sol, rxN_vid_eol, rxN_vid_sof, rxN_vid_eof, rxN_vid_locked, and rxN_vid_data.

The following table describes how to connect the CVI and DisplayPort sink signals.

Note: This example uses the Intel® Clocked Video Input IP.

Table 56. Connecting CVI Signals to DisplayPort Sink Stream 0 Signals
CVI Signal	DisplayPort Sink Signal	Comment
`vid_data`	`rx_vid_data`	Video data
`vid_datavalid`	–	Drive high because the video data is not oversampled.
`vid_f`	`rx_vid_field`	Drive low because the video data is progressive.
`vid_locked`	`rx_vid_locked`	The core asserts this signal when a stable stream is present.
`vid_de`	`rx_vid_valid`	Indicates the active picture region of a line.
`vid_h_sync`	`rx_vid_eol`	The `rx_vid_eol` signal generates the `vid_h_sync` pulse by delaying it (by 1 clock cycle) to appear in the horizontal blanking period after the active video ends (`rx_vid_valid` is deasserted).
`vid_v_sync`	`rx_vid_eof`	The `rx_vid_eof` signal generates the `vid_v_sync` pulse by delaying it (by 1 clock cycle) to appear in the vertical blanking period after the active video ends (`rx_vid_valid` is deasserted).

Verilog HDL CVI — DisplayPort Sink Example

// CVI V-sync and H-sync are derived from delayed versions of the eol and eof signals

always @ (posedge clk_video) 
begin 
	rx_vid_h_sync <= rx_vid_eol; 	
	rx_vid_v_sync <= rx_vid_eof; 
end

//datavalid is derived from rx_vid_valid and horizontal blanking signal.

always @ (posedge clk_video) 
begin 
	if (reset)
		h_blanking <= 1’b0;
	else
		h_blanking <= rx_vid_eol? 1’b1 : 
			      rx_vid_sol? 1’b0 :
			      h_blanking;
end 

assign vid_datavalid = (|rx_vid_valid) | h_blanking;

assign vid_data = rx_vid_data;

assign vid_f = 1’b0;

assign vid_locked = rx_vid_locked;

assign vid_h_sync = rx_vid_h_sync;

assign vid_de = rx_vid_valid;

assign vid_v_sync = rx_vid_v_sync;

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DisplayPort Intel® FPGA IP User Guide

6.6.6. Clocked Video Input Interface

Verilog HDL CVI — DisplayPort Sink Example