DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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8.1.3. View the Results

You can view the results in the ModelSim* GUI by loading various .do files in the Wave viewer.

  1. Launch the ModelSim* GUI with the vsim command.
  2. In the ModelSim* Tcl window, execute the dataset open command: dataset open vsim.wlf
  3. Select View > Open Wave files.
  4. Load the .do files to view the waveforms (refer back to Table 7-1 for a listing of the files).

    Figure 43. RX Reconfiguration WaveformIn the timing diagram below, rx_link_rate is set to 1 (HBR). When the core makes a request, the rx_reconfig_req port goes high. The user logic asserts rx_reconfig_ack and then reconfigures the transceiver. During reconfiguration, the user logic holds rx_reconfig_busy high; the user logic drives it low when reconfiguration completes.

    Figure 44. TX Reconfiguration WaveformIn the timing diagram below, tx_link_rate is set to 1 (HBR). When the core makes a request, the tx_reconfig_req port goes high. The user logic asserts tx_reconfig_ack and then reconfigures the transceiver. During reconfiguration, the user logic holds tx_reconfig_busy high; the user logic drives it low when reconfiguration completes.

    Figure 45. TX Analog Reconfiguration Waveform In the timing diagram below, tx_vod and tx_emp are both set to 00. When the core makes a request, the tx_analog_reconfig_req port goes high. The user logic asserts tx_analog_reconfig_ack and then reconfigures the transceiver. During reconfiguration, the user logic holds tx_analog_reconfig_busy high; the user logic drives it low when reconfiguration completes.

    Figure 46. RX Video WaveformThis timing diagram shows an example RX video waveform when interfacing to CVI. The rx_vid_eol signal generates the h_sync pulse by delaying it (by 1 clock cycle) to appear in the horizontal blanking period after the active video ends (VALID is deasserted). The rx_vid_eof signal generates the v_sync pulse by delaying it (by 1 clock cycle) to appear in the vertical blanking period after the active video ends (VALID is deasserted).