DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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5.8.2. AUX Interface

The IP has three ports that control the serial data across the AUX channel:

  • Data input (tx_aux_in)
  • Data output (tx_aux_out)
  • Output enable (tx_aux_oe). The output enable port controls the direction of data across the bidirectional link.

These ports are clocked by the source’s 16 MHz clock (aux_clk).

The source’s AUX controller captures all bytes sent from and received by the AUX channel, which is useful for debugging. The IP provides a standard stream interface that you can use to drive an Avalon-ST FIFO component directly.