DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

10.7. Source MST Registers

DPTX_MST_CONTROL1

Address: 0x00a0

Direction: RW

Table 100.  DPTX_MST_CONTROL1 Bits

Bit

Bit Name

Function

31 VCPTAB_UPD_FORCE

This flag always reads back at 0.

1 = Force VC payload ID table update
30 VCPTAB_UPD_REQ

This flag always reads back at 0.

1 = Request for VC payload ID table update

29:20 Unused  
19:16 VCP_ID3

VC payload ID for Stream 3

15:12 VCP_ID2

VC payload ID for Stream 2

11:8 VCP_ID1

VC payload ID for Stream 1

7:4 VCP_ID0

VC payload ID for Stream 0

3:1 Unused  
0 MST_EN

8B/10B Channel Coding:

Enable or disable MST

  • 1 = MST framing
  • 0 = SST framing

128B/132B Channel Coding:

Reserved

When you assert VCPTAB_UPD_FORCE, the source forces the VC payload table contained in DPTX_MST_VCPTAB0 through DPTX_MST_VCPTAB7 to be taken immediately into use. No ACT sequence is generated in this case.

When you assert VCPTAB_UPD_REQ, the source requests to generate an ACT sequence and after that, use the VC payload table contained in DPTX_MST_VCPTAB0 through DPTX_MST_VCPTAB7.