DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
Public

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10.8.5. DPTX_AUX_BYTE2

AUX Transaction Byte 2 Register.

Address: 0x0104

Direction: RW

Reset: 0x00000000

Table 114.  DPTX_AUX_BYTE2 Bits

Bit

Bit Name

Function

31:8

Unused

7:0

BYTE

Transaction length[3:0] for the next request, or data(2) received in the last reply (refer to the VESA DisplayPort Standard for details)