DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
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11.7. Sink Audio Registers

The audio registers are allocated at addresses:

  • 0×0030 through 0×003f for Stream 0
  • 0×0050 through 0×005f for Stream 1
  • 0×0070 through 0×007f for Stream 2
  • 0×0090 through 0×009f for Stream 3
Note: Only registers for Stream 0 are listed in the following sections.