DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 9/02/2022
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10.5. Source CRC Registers

The CRC registers are allocated at addresses:

  • 0x00BA through 0x00BC for Stream 0
  • 0x00CA through 0x00CC for Stream 1
  • 0x00DA through 0x00DC for Stream 2
  • 0x00EA through 0x00EC for Stream 3
Note: Only registers for Stream 0 are listed in the following sections.

DPTX0_CRC_R

Address: 0x00BA

Direction: RO

Reset: 0x00000000

Table 96.  DPTX0_CRC_R Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_R

Input video CRC for the red component

DPTX0_CRC_G

Address: 0x00BB

Direction: RO

Reset: 0x00000000

Table 97.  DPTX0_CRC_G Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_G

Input video CRC for the green component

DPTX0_CRC_B

Address: 0x00BC

Direction: RO

Reset: 0x00000000

Table 98.  DPTX0_CRC_B Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_B

Input video CRC for the blue component