Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

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Date 3/28/2022
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1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Developing Your Intel® Arria® 10 Custom Platform 3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.3. Contents of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases
1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform x
1.2.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Board Variants
1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases x
1.4.1. BSP Changes from Intel® Quartus® Prime Design Suite Version 16.1 to Version 17.0 1.4.2. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.0 to Version 17.1 1.4.3. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.1 to Version 18.0 1.4.4. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.0 to Version 18.1 1.4.5. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.1 to Version 19.1
2. Developing Your Intel® Arria® 10 Custom Platform x
2.1. Initializing Your Intel® Arria® 10 Custom Platform 2.2. Modifying the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 2.3. Integrating Your Intel® Arria® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Intel® Arria® 10 Custom Platform Software Development Environment 2.5. Establishing Intel® Arria® 10 Custom Platform Host Communication 2.6. Branding Your Intel® Arria® 10 Custom Platform 2.7. Changing the Device Part Number 2.8. Connecting the Memory in the Intel® Arria® 10 Custom Platform 2.9. Modifying the Kernel PLL Reference Clock 2.10. Integrating an OpenCL Kernel in Your Intel® Arria® 10 Custom Platform 2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform 2.12. Troubleshooting Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Issues
2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform x
2.11.1. Generating the base.qar Post-Fit Netlist for Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture x
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® 3.2. DDR4 as Global Memory for OpenCL Applications 3.3. Host Connection to OpenCL Kernels 3.4. Intel® Arria® 10 FPGA System Design 3.5. Dynamic PLL Reconfiguration 3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 3.7. Intel® Quartus® Prime Compilation Flow and Scripts 3.8. Addition of Timing Constraints 3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.10. Intel® Arria® 10 FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 3.13. Intel® Arria® 10 FPGA Development Kit Reference Platform Scripts 3.14. Considerations in Intel® Arria® 10 GX FPGA Development Kit Reference Platform Implementation
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® x
3.1.1. Instantiation of Intel® Arria® 10 PCIe* Hard IP with Direct Memory Access 3.1.2. Device Identification Registers for Intel® Arria® 10 PCIe Hard IP 3.1.3. Instantiation of the version_id Component 3.1.4. Definitions of Intel® Arria® 10 FPGA Development Kit Reference Platform Hardware Constraints in Software Headers Files 3.1.5. PCIe Kernel Driver for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 3.1.6. Direct Memory Access 3.1.7. Message Signaled Interrupt 3.1.8. Partial Reconfiguration 3.1.9. Cable Autodetect 3.1.10. Host Channel
3.1.6. Direct Memory Access x
3.1.6.1. Implementing a DMA Transfer
3.1.10. Host Channel x
3.1.10.1. Host Channel IP Instantiation 3.1.10.2. Host Channel Top Connection to PCIe* DMA 3.1.10.3. Host Channel Top Connection to OpenCL Kernel
3.2. DDR4 as Global Memory for OpenCL Applications x
3.2.1. DDR4 IP Instantiation 3.2.2. DDR4 Connection to PCIe Host 3.2.3. DDR4 Connection to the OpenCL Kernel
3.4. Intel® Arria® 10 FPGA System Design x
3.4.1. Clocks 3.4.2. Resets 3.4.3. Floorplan 3.4.4. Global Routing 3.4.5. Pipelining 3.4.6. DDR4 Calibration 3.4.7. Kernel Reprogramming via Partial Reconfiguration
3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design x
3.6.1. Supply the Kernel Clock 3.6.2. Guarantee Kernel Clock Timing 3.6.3. Provide a Timing-Closed Post-Fit Netlist
3.7. Intel® Quartus® Prime Compilation Flow and Scripts x
3.7.1. Enabling the Intel® Quartus® Prime Forward-Compatibility Flow 3.7.2. Intel® Quartus® Prime Compilation Flow for Board Developers 3.7.3. Intel® Quartus® Prime Compilation Flow for Custom Platform Users 3.7.4. Platform Designer System Generation 3.7.5. QDB File Generation 3.7.6. Hash Checking
3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
3.10. Intel® Arria® 10 FPGA Programming Flow x
3.10.1. Define the Contents of the fpga.bin File for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
3.12.5. aocl diagnose x
3.12.5.1. Possible Errors After Running the diagnose Utility
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Developing Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

Table 20.  Document Revision History of the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
Document Version Intel® Quartus® Prime Version Changes
2022.03.28 19.1
  • Updated the terms master and slave to host and agent, respectively.
2019.04.18 19.1
2019.02.11 18.1
Table 21.  Document Revision History of the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
Date Version Changes
November 2017 2017.11.03
May 2017 2017.05.08 Replaced references to ACL_QSH_COMPILE_CMD with ACL_DEFAULT_FLOW.
October 2016 2016.10.31
  • Rebranded Altera SDK for OpenCL to Intel® FPGA SDK for OpenCL™ .
  • Rebranded Altera Offline Compiler to Intel® FPGA SDK for OpenCL™ Offline Compiler.
  • Changed the short-form name of the Reference Platform from altera_a10pciedk to a10_ref, to match the directory name in the SDK.
  • Added notice that you must contact your field applications engineer or regional support center representative to configure the Arria 10 GX FPGA Development Kit before using it with the SDK.
  • Removed the a10gx_es2 and the a10gx_es3 board variants from the Reference Platform. The a10_ref Reference Platform only supports the a10gx board variant.
  • In Contents of the Arria 10 GX FPGA Development Kit Reference Platform:
    • For Windows, changed the source_windows64 directory to source.
    • Updated the list of files available in the a10gx subdirectory.
    • Removed information for the max5_133.pof file.
  • Removed statement regarding PR being an early-access feature.
  • Updated the location of the acl_ddr4_a10.qsys and acl_ddr4_a10_core.qsys files from the a10gx/ip directory to the top-level a10gx directory. The board.qsys, acl_ddr4_a10.qsys, and acl_ddr4_a10_core.qsys systems were migrated to Qsys Pro.
  • In the ip subdirectory, added .ip files that contain parameters of instantiated external OpenCL IP. Refer to Contents of the Arria 10 GX FPGA Development Kit Reference Platform for more information.
  • Added an opencl_bsp_ip.qsf file so that qsys_archive in Qsys Pro can insert .qsys and .ip files into this revision. All Verilog and Qsys source files from top.sdc and top_post.sdc are now in opencl_bsp_ip.qsf.
  • In Modifying the Arria 10 GX FPGA Development Kit Reference Platform Design, added a step to update the device.tcl file with the correct settings.
  • In Changing the Device Part Number:
    • Noted that the QSF setting for the device part number is now in device.tcl instead of flat.qsf The following device-specific assignments are now in device.tcl:
      • FAMILY, MIN_CORE_JUNCTION_TEMP, MAX_CORE_JUNCTION_TEMP, DEVICE_FILTER_PACKAGE, DEVICE_FILTER_PIN_COUNT, ERROR_CHECK_FREQUENCY_DIVISOR, STRATIX_DEVICE_IO_STANDARD, RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP, RESERVE_DATA0_AFTER_CONFIGURATION
    • Noted that the device part number must be updated in acl_ddr4_a10.qsys and acl_ddr4_a10_core.qsys, in addition to board.qsys.
  • In Guaranteeing Timing Closure in the Arria 10 Custom Platform and Generating the base.qdb Post-Fit Netlist for Your Arria 10 Custom Platform, noted that base.sdc must be copied along with base.qdb and pr_base_id.txt into the Custom Platform.
  • In Floorplan, updated the floorplan of the a10_ref Reference Platform.
  • In Provide a Timing-Closed Post-Fit Netlist, removed the QSF assignments that enabled the Spectra-Q engine compilation flow for base and top revision compilations. The base.qsf file no longer needs to be updated in order to enable the flow.
  • In Enabling the Quartus Prime Spectra-Q Forward_Compatibility Flow:
    • Modified the Quartus Prime software command to be added to the post_flow_pr.tcl script to generate the forward-compatible base.qdb file.
    • Removed the step of modifying the quartus.ini file because it is no longer needed.
  • In Quartus Prime Compilation Flow for Board Developers, modified the list of tasks that are performed when the quartus_sh --flow compile top -c base command was invoked because the process would no longer run the pre_flow_pr.tcl script.
  • In the top.qpf file, reorganized the order of the revisions to opencl_bsp_ip, flat, base, top_synth, and then top. In addition , removed old references to Intel® Quartus® Prime software version 15.1
  • Modified top_post.sdc file to reflect Qsys Pro RTL hierarchy changes
  • To facilitate Partial Reconfiguration:
    • Added set_global_assignment -name REVISION_TYPE PR_BASE to the base.qsf file
    • Added set_global_assignment -name REVISION_TYPE PR_BASE to the top_synth.qsf file
    • Added set_global_assignment -name REVISION_TYPE PR_IMPL to the top.qsf file
    • In the quartus.ini file, removed the following lines:
      • qhd_enable_pr_bak_export=on
      • pr_allow_lims_on_globals_user_guarantee_frozen_high=on
      • apl_use_advanced_pcl=off
      • qhd_force_bak_export=on and
      • hd_force_bak_import=on
  • In the flat.qsf file:
    • Removed the wildcarded LREGION assignments for pipe_stage_dma* and pipe_stage_pcie_* and the commented GLOBAL_SIGNAL assignments.
    • Added the line PR_ALLOW_GLOBAL_LIMS ON -to freeze_wrapper_inst|kernel_system_clock_reset_reset_reset_n
    • Changed the GLOBAL_SIGNAL assignment to kernel clocks
July 2016 2016.07.29
  • Maintenance release.
  • In Arria 10 GX FPGA Development Kit Reference Platform Board Variants and Initializing Your Arria 10 Custom Platform, added reminder to match the board variant with the status of the Arria® 10 device on your board.
May 2016 2016.05.09
  • Modified content to reflect the creation of the base.qdb file in lieu of the base_qhd.qar file.
  • Modified content to reflect the implementation of the flat.qsf file, which contains all the common QSF assignments shared among the base.qsf, top.qsf, and top_synth.qsf files. Use the flat revision for compilation flows that cannot use PR and do not require guaranteed timing. Because the flat revision is included in both the base and top revisions, use the flat revision to expand your design (for example, to attach extra DDR memory banks on your board).
  • Modified content to reflect the updated functionality of the pre_flow_pr.tcl and post_flow_pr.tcl scripts.
  • Updated the command you run to execute the base revision compilation

    from quartus_sh -t base_compile.tcl

    to quartus_sh --flow compile top -c base.

    This update enables you to compile the design from the Quartus Prime Pro Edition software GUI.

  • Removed the ip/acl_kernel_clk_a10/acl_kernel_clk_a10.qsys and ip/acl_temperature_a10/<file_name> files from the Reference Platform because the acl_kernel_clk_a10 and acl_temperature_sensor_a10 IP are now part of the Altera SDK for OpenCL.

    Use the IPs from AOCL instead of duplicating them in your Custom Platform. A check is in place to verify that these IPs are not duplicated in your Custom Platform.

  • The guaranteed timing flow is now part of AOCL. To avoid duplication, removed the following files from the Reference Platform:
    • adjust_plls.tcl, which creates the PLL configuration file and modifies the PLL atoms
    • pr_checks.tcl, which checks for initialized MLABs
  • Removed information on the following legacy files; they are no longer part of the Reference Platform:
    • hardware/<board_name>/base_compile.tcl
    • hardware/<board_name>/base_qhd.qar
    • hardware/<board_name>/system.qsys
    • scripts/call_script_as_function.tcl
    • scripts/create_pr_base_id.tcl
  • Added memory hierarchy in board.qsys:
    • The DDR4 subsystem is now in a separate IP located in the ip/acl_ddr4_a10 directory
    • The DDR4 core and pipeline stages are not in separate Qsys systems
  • In Describe the Arria 10 GX FPGA Development Kit Reference Platform Hardware to the AOCL, updated the example Fitter Partition Statistics report and the explanation on how to calculate used_resources for alms.
  • Under Quartus Prime Compilation Flow and Scripts, added the section Enabling the Quartus Prime Spectra-Q Forward-Compatibility Flow.

    Modified the import_compile.tcl file and added INI settings to quartus.ini and base.qsf to enable the Forward Compatibility flow. Support for the Forward Compatibility flow is preliminary. Refer to the Altera SDK for OpenCL version 16.0 Release Notes for more details.

December 2015 2015.12.21 Initial release.
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