Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.4.7. Kernel Reprogramming via Partial Reconfiguration

The Intel® Arria® 10 GX FPGA Development Kit Reference Platform provides the ability to modify the OpenCL™ kernel and reprograms it onto the FPGA. The a10_ref Reference Platform places the OpenCL kernel in a PR region of the device. Doing so allows you to reprogram the kernel-specific portion of the FPGA across the PCIe bus without affecting the board interface region (that is, static region) of the device.


Intel® Quartus® Prime Pro Edition software's Partial Reconfiguration feature

To ensure that the device functions properly during and after PR reprogramming, following these rules:

  • Place a freeze wrapper around the PR region. The freeze wrapper holds the critical control outputs from the PR region in a known, inactive state during the reprogramming of the logic inside the PR region.

    The INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/ip/freeze_wrapper.v file implements the freeze wrapper, where INTELFPGAOCLSDKROOT is the path to the SDK installation.

  • Hold the kernel_reset_n signal, which is routed using Global Clock resources, in a logic 1 (deasserted) state during reprogramming of the PR region. When programming completes, assert the kernel_reset_n signal (that is, set it to the low state) before disabling the freeze wrapper. Asserting the kernel_reset_n signal resets all logic in the PR region to a known state. This assertion step is necessary because the state of all flipflops in the PR region is undefined after PR programming. The logic in the freeze_wrapper.v file implements the required behavior for the reset and freeze signals.