Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.7.6. Hash Checking

Intel® assigns a unique ID to each base revision compilation to ensure a safe way of only partially reconfiguring a PR region on top of a design that has a matching static region.

The unique ID is generated at the beginning of a base revision compilation using the MD5 message-digest algorithm. The MD5 algorithm generates a hash of a text file that contains the current working directory and a high-resolution timer value. The MD5 algorithm then truncates the hash to a 32-bit value. The INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/scripts/pre_flow_pr.tcl script stores this 32-bit value in the pr_base_id register IP within the board.qsys Platform Designer system by overwriting the default value of 0xdeadbeef.

The unique ID for the base revision compilation is added to the file. The ID becomes part of the import revision compilation directory after the file is copied from the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx directory. During the fpga.bin generation step of the import revision compilation, the unique ID is added as the .acl.hash section of the fpga.bin file.

When the Intel® FPGA SDK for OpenCL™ user invokes the aocl program utility to reconfigure the FPGA, the software first checks that the pr_base id value in the currently programmed static region matches the hash value in the fpga.bin section within the .aocx file. If the two 32-bit values match, it is safe to execute partial reconfiguration. If the 32-bit values do not match, the aocl program utility performs full-chip JTAG programming via Intel® FPGA Download Cable.