Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.5. Dynamic PLL Reconfiguration

PLL that is used to generate the OpenCL kernel clocks resides in the static region of the design's floorplan. As a result, reprogramming of the kernel partition via PR does not modify the PLL settings. The Intel® FPGA SDK for OpenCL™ relies on the post_flow_pr.tcl Tcl script and the instantiation of the acl_kernel_clk_a10 Platform Designer component to modify kernel PLL.

In both PR reprogramming and full-chip JTAG programming, the PLL is dynamically reconfigured by default after FPGA configuration completes. This default dynamic PLL reconfiguration step is unnecessary after full-chip programming because the correct PLL settings are already part of the .sof file programmed onto the FPGA over JTAG.

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