Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.6.3. Provide a Timing-Closed Post-Fit Netlist

Each Intel® FPGA SDK for OpenCL™ -compatible Reference and Custom Platform, such as the Intel® Arria® 10 GX FPGA Development Kit Reference Platform, provides a timing-closed post-fit netlist that imports placement and routing information for all nodes clocked by non-kernel clocks.


Intel® Quartus® Prime Pro Edition compiler

Intel® Quartus® Prime software provides several mechanisms for preserving the placement and routing of some previously compiled logic and importing this logic into a new compilation. For Intel® Arria® 10 devices, the previously compiled logic is imported into the compilation flow.

Figure 3. Custom Platform Development Flow and Hand-Off between Board Developer and SDK End UserThe board developer is responsible for porting the a10_ref Reference Platform to their own board, closing timing, and locking down the static part of the board.
Figure 4. Structure of the Hierarchy for the OpenCL Hardware System on the Intel® Arria® 10 DeviceThis figure illustrates that the placement and routing for everything outside the kernel_system partition are preserved and are imported in the top revision compilations. The kernel_system partition itself is not preserved and is compiled from source.

The Intel® Quartus® Prime Pro Edition compilation flow can preserve the placement and routing of the board interface partition via the exported Intel® Quartus® Prime Archive File. The base.qdb file contains all the database files for the base compilation of root_partition. The a10_ref Reference Platform is configured with the project revisions and partitioning that are necessary to implement the compilation flow. By default, the SDK invokes the Intel® Quartus® Prime Pro Edition software on the top revision. This revision is configured to import and restore the base.qdb file, which has been pre-compiled and exported from a base revision compilation.

When developing your Custom Platform from the a10_ref Reference Platform, it is essential to maintain the flat.qsf, base.qsf, top.qsf, and top_synth.qsf Intel® Quartus® Prime Settings Files.

The a10_ref Reference Platform includes two additional partitions: the Top partition and the kernel_system partition. The Top partition contains all logic, and the kernel_system partition contains the logic in the PR region. The PR region is specified by the following assignments:

set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to freeze_wrapper_inst|kernel_system_inst