Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

2.11.1. Generating the base.qar Post-Fit Netlist for Your Intel® Arria® 10 Custom Platform

To implement the compilation flow, you must generate a base.qar Intel® Quartus® Prime Archive File for your Intel® Arria® 10 Custom Platform.
Following steps represent a general procedure for regenerating the base.qar file:
  1. Port the system design and the flat.qsf file to your computing card.
  2. Compile the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/ kernel source file using the base revision. Fix any timing failures and recompile the kernel until timing is clean. You can add the -bsp-flow=base argument to the aoc command to generate the base.qar file during the kernel compilation.
    INTELFPGAOCLSDKROOT points to the location of the Intel® FPGA SDK for OpenCL™ installation.
  3. Copy the generated base.qar file into your Custom Platform.
  4. Using the default compilation flow, test the base.qar file across several OpenCL™ design examples and confirm that the following criteria are satisfied:
    • All compilations close timing.
    • The OpenCL design examples achieve satisfactory Fmax.
    • The OpenCL design examples function on the accelerator board.