ID 683267
Date 3/28/2022
Public

## 3.6.1. Supply the Kernel Clock

In the Intel® Arria® 10 GX FPGA Development Kit Reference Platform, the OpenCL™ Kernel Clock Generator component provides the kernel clock and its 2x variant.

The REF_CLK_RATE parameter specifies the frequency of the reference clock that connects to the kernel PLL (pll_refclk). For the a10_ref Reference Platform, the REF_CLK_RATE frequency is 125 MHz.

The KERNEL_TARGET_CLOCK_RATE parameter specifies the frequency that the Intel® Quartus® Prime Pro Edition software attempts to achieve during compilation. The board hardware contains some logic that the kernel clock clocks. At a minimum, the board hardware includes the clock crossing hardware. To prevent this logic from limiting the Fmax achievable by a kernel, the KERNEL_TARGET_CLOCK_RATE must be higher than the frequency that a simple kernel can achieve on your device. For the Intel® Arria® 10 GX FPGA Development Kit that the a10_ref Reference Platform targets, the KERNEL_TARGET_CLOCK_RATE is 400 MHz.

CAUTION:

When developing a Custom Platform, setting a high target Fmax might cause difficulty in achieving timing closure.

When developing your Custom Platform and attempting to close timing, add an overriding SDC definition to relax the timing of the kernel. The following code example from the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/top_post.sdc file applies a 5 ns (200 MHz) maximum delay constraint on the OpenCL kernel during base revision compilations:


if {! [string equal $::TimeQuestInfo(nameofexecutable) "quartus_map"]} { if { [get_current_revision] eq "base" } { post_message -type critical_warning "Compiling with slowed OpenCL Kernel clock. This is to help achieve timing closure for board bringup." if {! [string equal$::TimeQuestInfo(nameofexecutable) "quartus_sta"]}
{
set kernel_keepers [get_keepers system_inst\|kernel_system\|*]
set_max_delay 5 -from $kernel_keepers -to$kernel_keepers
}
}
}