Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform

When modifying the Intel® Arria® 10 GX FPGA Development Kit Reference Platform into your own Custom Platform, ensure that guaranteed timing closure holds true for your Custom Platform.
  1. Establish the floorplan of your design.
    Important: Consider all design criteria outlined in the FPGA System Design section of the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.
  2. Compile several seeds of the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/ file until you generate a design that closes timing cleanly.
    To specify the seed number, include the -seed=<N> option in your aoc command.
  3. Copy the base.qar file from the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx directory into your Custom Platform.
  4. Use the flat.qsf file in the a10_ref Reference Platform as references to determine the type of information you must include in the flat.qsf file for your Custom Platform.
    The base.qsf, top.qsf, and top_synth.qsf files automatically inherit all settings in the flat.qsf file. However, if you need to modify Logic Lock Plus region or PR assignments, only make these changes in the base.qsf file.
  5. Confirm that you can use the .aocx file to reprogram the FPGA by invoking the aocl program acl0 boardtest.aocx command.
  6. Remove the ACL_DEFAULT_FLOW environment variable that you added when integrating your Custom Platform with the Intel® FPGA SDK for OpenCL™ .
  7. Ensure that the environment variable CL_CONTEXT_COMPILER_MODE_INTELFPGA is not set.
  8. Run the boardtest_host executable.