1.3. Contents of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
|Windows File or Folder||Linux File or Directory||Description|
|board_env.xml||board_env.xml||eXtensible Markup Language (XML) file that describes the Reference Platform to the Intel® FPGA SDK for OpenCL™ .|
|hardware||hardware||Contains the Intel® Quartus® Prime project templates for the a10gx board variant.
See Contents of the a10gx Directory for a list of files in this directory.
|windows64||linux64||Contains the MMD library, kernel mode driver, and executable files of the SDK utilities (that is, install, uninstall, flash, program, diagnose) for your 64-bit operating system.|
For Windows, the source folder contains source codes for the MMD library and SDK utilities. The MMD library and the SDK utilities are in the windows64 folder.
For Linux, the source directory contains source codes for the MMD library and SDK utilities. The MMD library and the SDK utilities are in the linux64 directory.
|mem.qsys||Platform Designer system that, together with the .ip files in the ip/mem subdirectory, implements the mem component.|
|ddr4.qsys||Platform Designer system that, together with the .ip files in the ip/ddr4 subdirectory, implements the ddr4 component.|
|base.qsf|| Intel® Quartus® Prime Settings File for the base project revision. This file includes, by reference, all the settings in the flat.qsf file.
Use this revision when porting the a10_ref Reference Platform to your own Custom Platform. The Intel® Quartus® Prime Pro Edition software compiles this base project revision from source code.
|base.qar|| Intel® Quartus® Prime Archive File that contains base.qdb, pr_base.id, and base.sdc. This file is generated by the scripts/post_flow_pr.tcl file during base revision compile, and is used during import revision compilation.
|board.qsys||Platform Designer system that implements the board interfaces (that is, the static region) of the OpenCL hardware system.|
|board_spec.xml||XML file that provides the definition of the board hardware interfaces to the SDK.|
|device.tcl||Tcl file that is included in all revisions and contains all device-specific information (for example, device family, ordering part number (OPN), and voltage settings).|
|flat.qsf|| Intel® Quartus® Prime Settings File for the flat project revision. This file includes all the common settings, such as pin location assignments, that are used in the other revisions of the project (that is, base, top, and top_synth). The base.qsf, top.qsf, and top_synth.qsf files include, by reference, all the settings in the flat.qsf file.
The Intel® Quartus® Prime software compiles the flat revision with minimal location constraints. The flat revision compilation does not generate a base.qar file that you can use for future import compilations and does not implement the guaranteed timing flow.
|import_compile.tcl||Tcl script for the SDK-user compilation flow (that is, import revision compilation).|
|max5_150.pof||Programming file for the MAX® V device on the Intel® Arria® 10 GX FPGA Development Kit that sets the memory reference clock to 150 MHz by default at power-up.
You must program the max5_150.pof file onto your a10gx board.
|opencl_bsp_ip.qsf|| Intel® Quartus® Prime Settings File that collects all the required .ip files in a unique location.
During flat and base revision compilations, the board.qsys, mem.qsys and ddr4.qsys Platform Designer files are added to the opencl_bsp_ip.qsf file.
|reset_2x.sdc||Synopsys Design Constraints file with timing constraints for reset synchronizers on the 2x kernel clock.|
|quartus.ini||Contains any special Intel® Quartus® Prime software options that you need to compile OpenCL kernels for the a10_ref Reference Platform.|
|top.qpf||Intel® Quartus® Prime Project File for the OpenCL hardware system.|
|top.qsf||Intel® Quartus® Prime Settings File for the SDK-user compilation flow.|
|top.sdc||Synopsys Design Constraints file that contains board-specific timing constraints.|
|top.v||Top-level Verilog Design file for the OpenCL hardware system.|
|top_post.sdc||Platform Designer and Intel® FPGA SDK for OpenCL™ IP-specific timing constraints.|
|top_synth.qsf||Intel® Quartus® Prime Settings File for the Intel® Quartus® Prime revision in which the OpenCL kernel system is synthesized.|
|ip/mem/<file_name>||Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the mem component.
You must provide both the mem.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.
|ip/ddr4/<file_name>||Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the ddr4 component.
You must provide both the ddr4.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.
|ip/board/<file_name>||Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the board instance.
You must provide both the board.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.
|ip/freeze_wrapper.v||Verilog Design File that implements the freeze logic placed at outputs of the Partial Reconfiguration region.|
|ip/irq_controller/<file_name>||IP that receives interrupts from the OpenCL kernel system and sends message signaled interrupts (MSI) to the host.
Refer to the Message Signaled Interrupts section for more information.
|ip/host_channel||IP that implements the DMA descriptor controller as well as AVMM-to-AVST and AVST-to-AVMM between DMA and kernel.
Attention: This IP is available only in the a10gx_hostch board variant.
|scripts/base_write_sdc.tcl||Tcl script that the base revision compilation uses to generate the base.sdc file containing all the constraints collected in the base revision compilation. The Intel® Quartus® Prime Pro Edition software uses the base.sdc file when compiling the import (top) revision.|
|scripts/create_fpga_bin_pr.tcl||Tcl script that generates the fpga.bin file. The fpga.bin file contains all the necessary files for configuring the FPGA.
For more information on the fpga.bin file, refer to the Define the Contents of the fpga.bin File for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform section.
|scripts/post_flow_pr.tcl||Tcl script that implements the guaranteed timing closure flow, as described in the Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design section.|
|scripts/pre_flow_pr.tcl||Tcl script that executes before the invocation of the Intel® Quartus® Prime software compilation. Running the script generates the Platform Designer HDL for board.qsys and kernel_system.qsys. It also creates a unique ID for the PR base revision (that is, static region). This unique ID is stored in the pr_base.id file.|
|scripts/regenerate_cache.tcl||Tcl script that regenerates the BAK cache file in your temporary directory.|
|scripts/qar_ip_files.tcl||Tcl script that packages up base.qdb, pr_base.id and base.sdc during base revision compile.|
|scripts/create_acds_ver_hex.tcl||Tcl script called by the pre_flow_pr.tcl script to create contents of the ACDS version ROM.|
Did you find the information on this page useful?