- 3.1.4. Definitions of Intel® Arria® 10 FPGA Development Kit Reference Platform Hardware Constraints in Software Headers Files
- 3.9.1. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™
3.7.3. Intel® Quartus® Prime Compilation Flow for Custom Platform Users
The import_compile.tcl script executes the following tasks:
- Runs the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/scripts/pre_flow_pr.tcl file. The pre_flow_pr.tcl script generates the board.qsys and the kernel_system.qsys Platform Designer System Files.
Refer to the Platform Designer System Generation section for more information.
- Imports the base revision compilation results as a .qdb file.
Refer to the QDB File Generation section for more information.
- Runs quartus_fit and quartus_asm to verify that the .qdb file is forward compatible.
- Runs quartus_syn to execute the Analysis and Synthesis stage of the Intel® Quartus® Prime compilation flow for the kernel partition only.
- Runs quartus_fit to execute the Place and Route stage of the Intel® Quartus® Prime compilation flow for the entire design.
- Runs quartus_sta to execute the static timing analysis stage of the Intel® Quartus® Prime compilation flow.
- Runs the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/scripts/post_flow_pr.tcl file. The post_flow_pr.tcl script determines the maximum frequency at which the OpenCL™ kernel can run and generates the corresponding PLL settings. The script then reruns the static timing analysis.
- Runs quartus_asm to generate the full-chip programming files for the base revision.
- Runs quartus_asm to generate the full-chip programming files for the import revision.
- Generates the fpga.bin file, which contains the following files and IDs:
- The top.sof full-chip programming file.
- The top.rbf PR programming file.
- The pr_base.id unique ID for PR base revision.
Before quartus_asm generates the .sof file in an import revision compilation, the static region of the import revision compilation is compared to the static region of the base revision compilation to check for errors. To prevent a mismatch error in the I/O configuration shift register (IOCSR) bits, the PLL settings in the base.sof and top.sof files must be identical. When designing the Intel® Arria® 10 FPGA Development Kit Reference Platform, Intel® ensured in the import_compile.tcl Tcl script that the PLL settings in both the base.sof file and the top.sof file are identical, resulting in an additional quartus_asm execution step to regenerate the base.sof file.
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