Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Public
Document Table of Contents

1.4.2. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.0 to Version 17.1

If you use or have modified an Intel® Arria® 10 GX FPGA Development Kit Reference Platform BSP provided for Intel® Quartus® Prime Design Suite Version 17.0, review the following information to learn about changes implemented in the BSP for Version 17.1.

The files in the BSP have the following changes from Intel® Quartus® Prime Design Suite Version 17.0 to Version 17.1:

Table 4.  Changes in a10_ref Reference Platform from 17.0 to 17.1
File Change
acl_ddr4_a10_core.qsys Renamed as ddr4.qsys to reduce long path issues in Windows.
All .ip files in the ip/acl_ddr4_a10_core/directory Renamed as ip/ddr4/ to reduce long path issues in Windows.
acl_ddr4_a10.qsys Renamed as mem.qsys to reduce long path issues in Windows.
All .ip files in the ip/acl_ddr4_a10/directory Renamed as ip/mem/ to reduce long path issues in Windows.
board.qsys
  • Added ACDS version ROM.
  • Updated board interface version ID.
base.qsf Changed the hierarchy for Logic Lock regions due to the renaming of .qsys files.
flat.qsf
  • Added path to ACDS version ROM memory initialization file (MIF).
  • Changed the hierarchy for global signal due to the renaming of .qsys files.
  • Removed GENERATE_RBF_FILE ON assignment.
top.qsf Added GENERATE_PR_RBF_FILE ON and QDB_FILE_PARTITION assignments.
top_post.sdc Changed the hierarchy of asynchronous clock groups and false path due to the renaming of.qsys files.
import_compiles.tcl
  • Rebranded ALTERA to INTEL.
  • Updated the file for incremental and fast compile features.
board_spec.xml Updated version from 17.0 to 17.1
quartus.ini
  • Removed bak_eco_a10_pcie_1602_1611=on INI
  • Added qhd_skip_pr_revision_type_check=on INI
base.qar Updated the file with ACDS 17.1 static region.
scripts/pre_flow_pr.tcl
  • Rebranded ALTERA to INTEL.
  • Added a call to create_acds_ver_hex.tcl for ACDS version ROM.
  • Updated pr_base.id file also in flat revision compiles so that the unique flat compiles can be identified.
scripts/post_flow_pr.tcl
  • Rebranded ALTERA to INTEL.
  • Updated the file to enable fast compiles and update ACDS version ROM
  • Removed manual call to quartus_cpf for creating partial reconfiguration programming file since it is now done automatically in the flow.
scripts/create_fpga_bin_pr.tcl
  • Rebranded ALTERA to INTEL.
  • Added the Quartus version as part of fpga.bin.
scripts/qar_ip_files.tcl
  • Rebranded ALTERA to INTEL.
  • Changes required for renaming .qsys files.
  • Changes required for moving other tcl scripts into Intel® FPGA SDK for OpenCL™ .
scripts/regenerate_cache.tcl Changes needed for moving bak_flow.tcl into Intel® FPGA SDK for OpenCL™
scripts/bak_flow.tcl Moved the script into Intel® FPGA SDK for OpenCL™ .
scripts/helpers.tcl Moved the script into Intel® FPGA SDK for OpenCL™ .
scripts/create_acds_ver_hex.tcl Added the script to create the contents of the ACDS version ROM.
ip/host_channel Added the IP for a10gx_hostch board variant.

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