These clock domains include:
- 250 MHz PCIe* clock
- 300 MHz DDR4 clock
- 50 MHz general clock (config_clk)
- 125 MHz kernel reference clock
- Kernel clock that can have any clock frequency
With the exception of the kernel clock, the a10_ref Reference Platform is responsible for the timing closure of these clocks. However, because the board design must clock cross all interfaces in the kernel clock domain, the board design also has logic in the kernel clock domain. It is crucial that this logic is minimal and achieves an Fmax higher than typical kernel performance.