Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.2.1. DDR4 IP Instantiation

The Intel® Arria® 10 GX FPGA Development Kit Reference Platform uses one DDR4 Controller IP to communicate with the physical memory.
Table 15.  DDR4 SDRAM Controller IP Configuration Settings
IP Parameter Configuration Setting
Timing Parameters As per the computing card's data specifications.
Avalon Width Power of 2 Currently, OpenCL™ does not support non-power-of-2 bus widths. As a result, the a10_ref Reference Platform uses the option that forces the DDR4 controller to power of 2. Use the additional pins of this x72 core for error checking between the memory controller and the physical module.
Byte Enable Support Enabled

Byte enable support is necessary in the core because the Intel® FPGA SDK for OpenCL™ requires byte-level granularity to all memories.

Performance Enabling the reordering of DDR4 memory accesses and a deeper command queue look-ahead depth might provide increased bandwidth for some OpenCL kernels. For a target application, adjust these and other parameters as necessary.
Note: Increasing the command queue look-ahead depth allows the DDR4 memory controller to reorder more memory accesses to increase efficiency, which improves overall memory throughput.
Debug Disabled for production.