Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.13. Intel® Arria® 10 FPGA Development Kit Reference Platform Scripts

The Intel® Arria® 10 FPGA Development Kit Reference Platform includes a number of Tcl scripts in its hardware/<board_name>/scripts directory.
Table 18.  Tcl Scripts within the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/scripts Directory
Script Description
base_write_sdc.tcl The post_flow_pr.tcl script runs this script during the base revision compilation. The base_write_sdc.tcl script then exports all the SDC constraints to the base.sdc file, which is part of the board directory.
create_fpga_bin_pr.tcl Creates the ELF binary file, fpga.bin, from the .sof file, the .rbf file, and the file.
post_flow_pr.tcl This script runs after every Intel® Quartus® Prime Pro Edition software compilation. It facilitates the guaranteed timing flow by setting the kernel clock PLL, generating a small report in the acl_quartus_report.txt file, and rerunning STA with the modified kernel clock settings.
pre_flow_pr.tcl This script generates the RTL of the top-level board.qsys Platform Designer system for the static region and the kernel_system.qsys Platform Designer system for the kernel PR region.
qar_ip_files.tcl Tcl script that packages up all IP files in the base revision compile to create base.qar.
create_acds_ver_hex.tcl Tcl script that creates and acds_version_rom.mif files. PR can be done only if the programmed AOCX was compiled from the same Quartus version as AOCX being programmed. is stored in AOCX so that at runtime, BSP can determine Quartus version of AOCX being programmed.

acds_version_rom.mif is used during compilation, to update the contents of on-chip memory in the SOF file.

regenerate_cache.tcl Tcl script that regenerates the BAK cache file in your temporary directory.