Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.2.2. DDR4 Connection to PCIe Host

Connect all global memory systems in the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the host via the OpenCL™ Memory Bank Divider component.

The DDR4 IP core has one bank where its width and address configurations match those of the DDR4 SDRAM. Intel® tunes the other parameters such as burst size, pending reads, and pipelining. These parameters are customizable for an end application or board design.

The Avalon® host interfaces from the OpenCL Memory Bank Divider component connect to their respective memory controllers. The Avalon® agent connects to the PCIe* and DMA IP core. Implementations of appropriate clock crossing and pipelining are based on the design floorplan and the clock domains specific to the computing card. The OpenCL Memory Bank Divider section in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide specifies the connection details of the snoop and memorg ports.

Important: Instruct the host to verify the successful calibration of the memory controller.

The INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/board.qsys Platform Designer system uses a custom UniPHY Status to AVS IP component to aggregate different UniPHY status conduits into a single Avalon® agent port named s. This agent port connects to the pipe_stage_host_ctrl component so that the PCIe host can access it.