- 3.1.4. Definitions of Intel® Arria® 10 FPGA Development Kit Reference Platform Hardware Constraints in Software Headers Files
- 3.9.1. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™
3.2.2. DDR4 Connection to PCIe Host
The DDR4 IP core has one bank where its width and address configurations match those of the DDR4 SDRAM. Intel® tunes the other parameters such as burst size, pending reads, and pipelining. These parameters are customizable for an end application or board design.
The Avalon® host interfaces from the OpenCL Memory Bank Divider component connect to their respective memory controllers. The Avalon® agent connects to the PCIe* and DMA IP core. Implementations of appropriate clock crossing and pipelining are based on the design floorplan and the clock domains specific to the computing card. The OpenCL Memory Bank Divider section in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide specifies the connection details of the snoop and memorg ports.
The INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/board.qsys Platform Designer system uses a custom UniPHY Status to AVS IP component to aggregate different UniPHY status conduits into a single Avalon® agent port named s. This agent port connects to the pipe_stage_host_ctrl component so that the PCIe host can access it.
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