Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.2. DDR4 as Global Memory for OpenCL Applications

The Intel® Arria® 10 GX FPGA Development Kit has one bank of 2GB x72 DDR4-2400 SDRAM. The DDR4 SDRAM is a daughtercard that is mounted to the development kit's HiLo connector.

In the current version of the a10_ref Reference Platform, all Platform Designer components related to the DDR4 global memory are now part of the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/acl_ddr4_a10.qsys Platform Designer subsystem within board.qsys. In addition, the location of the clock domain crossings has changed to increase the number of blocks operating in the slower PCIe* domain. With this modified structure, you can add multiple memories with different clock domains to the system.

If you have a Custom Platform that is ported from a previous version of the a10_ref Reference Platform, you have the option to modify your Custom Platform as described above. This modification is not mandatory.


DDR4 external memory interfaces

For more information about the DDR4 external memory interface IP, refer to the DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines section in External Memory Interface Handbook Volume 2: Design Guidelines.

To use the DDR4 SDRAM as global memory for Intel® FPGA SDK for OpenCL™ designs, you must instantiate the memory controller IP, connect the memory IP to the host, and connect the memory IP to the kernel.

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