Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683267
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Developing Your Intel® Arria® 10 Custom Platform 3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.3. Contents of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases
1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform x
1.2.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Board Variants
1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases x
1.4.1. BSP Changes from Intel® Quartus® Prime Design Suite Version 16.1 to Version 17.0 1.4.2. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.0 to Version 17.1 1.4.3. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.1 to Version 18.0 1.4.4. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.0 to Version 18.1 1.4.5. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.1 to Version 19.1
2. Developing Your Intel® Arria® 10 Custom Platform x
2.1. Initializing Your Intel® Arria® 10 Custom Platform 2.2. Modifying the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 2.3. Integrating Your Intel® Arria® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Intel® Arria® 10 Custom Platform Software Development Environment 2.5. Establishing Intel® Arria® 10 Custom Platform Host Communication 2.6. Branding Your Intel® Arria® 10 Custom Platform 2.7. Changing the Device Part Number 2.8. Connecting the Memory in the Intel® Arria® 10 Custom Platform 2.9. Modifying the Kernel PLL Reference Clock 2.10. Integrating an OpenCL Kernel in Your Intel® Arria® 10 Custom Platform 2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform 2.12. Troubleshooting Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Issues
2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform x
2.11.1. Generating the base.qar Post-Fit Netlist for Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture x
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® 3.2. DDR4 as Global Memory for OpenCL Applications 3.3. Host Connection to OpenCL Kernels 3.4. Intel® Arria® 10 FPGA System Design 3.5. Dynamic PLL Reconfiguration 3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 3.7. Intel® Quartus® Prime Compilation Flow and Scripts 3.8. Addition of Timing Constraints 3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.10. Intel® Arria® 10 FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 3.13. Intel® Arria® 10 FPGA Development Kit Reference Platform Scripts 3.14. Considerations in Intel® Arria® 10 GX FPGA Development Kit Reference Platform Implementation
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® x
3.1.1. Instantiation of Intel® Arria® 10 PCIe* Hard IP with Direct Memory Access 3.1.2. Device Identification Registers for Intel® Arria® 10 PCIe Hard IP 3.1.3. Instantiation of the version_id Component 3.1.4. Definitions of Intel® Arria® 10 FPGA Development Kit Reference Platform Hardware Constraints in Software Headers Files 3.1.5. PCIe Kernel Driver for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 3.1.6. Direct Memory Access 3.1.7. Message Signaled Interrupt 3.1.8. Partial Reconfiguration 3.1.9. Cable Autodetect 3.1.10. Host Channel
3.1.6. Direct Memory Access x
3.1.6.1. Implementing a DMA Transfer
3.1.10. Host Channel x
3.1.10.1. Host Channel IP Instantiation 3.1.10.2. Host Channel Top Connection to PCIe* DMA 3.1.10.3. Host Channel Top Connection to OpenCL Kernel
3.2. DDR4 as Global Memory for OpenCL Applications x
3.2.1. DDR4 IP Instantiation 3.2.2. DDR4 Connection to PCIe Host 3.2.3. DDR4 Connection to the OpenCL Kernel
3.4. Intel® Arria® 10 FPGA System Design x
3.4.1. Clocks 3.4.2. Resets 3.4.3. Floorplan 3.4.4. Global Routing 3.4.5. Pipelining 3.4.6. DDR4 Calibration 3.4.7. Kernel Reprogramming via Partial Reconfiguration
3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design x
3.6.1. Supply the Kernel Clock 3.6.2. Guarantee Kernel Clock Timing 3.6.3. Provide a Timing-Closed Post-Fit Netlist
3.7. Intel® Quartus® Prime Compilation Flow and Scripts x
3.7.1. Enabling the Intel® Quartus® Prime Forward-Compatibility Flow 3.7.2. Intel® Quartus® Prime Compilation Flow for Board Developers 3.7.3. Intel® Quartus® Prime Compilation Flow for Custom Platform Users 3.7.4. Platform Designer System Generation 3.7.5. QDB File Generation 3.7.6. Hash Checking
3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
3.10. Intel® Arria® 10 FPGA Programming Flow x
3.10.1. Define the Contents of the fpga.bin File for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
3.12.5. aocl diagnose x
3.12.5.1. Possible Errors After Running the diagnose Utility
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Developing Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

3.1.2. Device Identification Registers for Intel® Arria® 10 PCIe Hard IP

To build PCIe* hardware, you must set PCIe IDs related to the device hardware.
You can find these PCIe ID definitions in the PCIe controller instantiated in the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/board.qsys Platform Designer System File. These IDs are necessary in the driver and the SDK's programming flow.
Table 10.  Device Hardware-Related PCIe ID Registers
ID Register Name ID Provider Description Parameter Name in PCIe IP Core
Vendor ID PCI-SIG® Identifies the FPGA manufacturer.

Always set this register to 0x1172, which is the Intel® vendor ID.

vendor_id_hwtcl
Device ID Intel® Describes the PCIe configuration on the FPGA according to Intel® 's internal guideline.

Set the device ID to the device code of the FPGA on your accelerator board.

For the Intel® Arria® 10 GX FPGA Development Kit Reference Platform, set the Device ID register to 0x2494, which signifies Gen 3 speed, 8 lanes, Intel® Arria® 10 device family, and Avalon® -MM interface, respectively.

Refer to Intel® FPGA SDK for OpenCL™ 's Numbering Convention for PCIe* Hard IP Device ID for more information.

device_id_hwtcl
Revision ID   When setting this ID, ensure that it matches the following revision IDs:
  • For Windows, the revision ID specified for the DeviceList field in the <your_custom_platform>\windows64\driver\acl_boards_<your_custom_platform>.inf file.
  • For Linux, the revision ID specified for the ACL_PCI_REVISION variable in the <your_custom_platform>/linux64/driver/hw_pcie_constants.h file.
—
Class Code Intel®

The Intel® FPGA SDK for OpenCL™ utility checks the base class value to verify whether the board is an OpenCL™ device.

Do not modify the class code settings.

  • Base class: 0x12 for processing accelerator
  • Sub class: 0x00
  • Programming interface: 0x01
—
Subsystem Vendor ID Board vendor Identifies the manufacturer of the accelerator board.

Set this register to the vendor ID of manufacturer of your accelerator board. For the a10_ref Reference Platform, the subsystem vendor ID is 0x1172.

If you are a board vendor, set this register to your vendor ID.

subsystem_vendor_id_hwtcl
Subsystem Device ID Board vendor Identifies the accelerator board.

The SDK uses this ID to identify the board because the software might perform differently on different boards. If you create a Custom Platform that supports multiple boards, use this ID to distinguish between the boards. Alternatively, if you have multiple Custom Platforms, each supporting a single board, you can use this ID to distinguish between the Custom Platforms.

Important: Make this ID unique to your Custom Platform. For example, for the a10_ref Reference Platform, the ID is 0xA151.
subsystem_device_id_hwtcl

The kernel driver uses the Vendor ID, Subsystem Vendor ID and the Subsystem Device ID to identify the boards it supports. The SDK's programming flow checks the Device ID to ensure that it programs a device with a .aocx Intel® FPGA SDK for OpenCL™ Offline Compiler executable file targeting that specific device.

Table 11.   Intel® FPGA SDK for OpenCL™ 's Numbering Convention for PCIe* Hard IP Device ID
Location in ID Definition
15:14 RESERVED
13:12 Speed
  • 0 — Gen 1
  • 1 — Gen 2
  • 2 — Gen 3
  • 3 — Gen 4
11 RESERVED
10:8 Number of lanes
  • 0 — 1 lane
  • 1 — 2 lanes
  • 3 — 4 lanes
  • 4 — 8 lanes
  • 5 — 16 lanes
  • 6 — 32 lanes
7:4 Device family
  • 0 — Altera Stratix IV GX
  • 1 — Altera Arria II GX
  • 2 — Stratix II GX
  • 3 — Arria GX
  • 4 — Cyclone IV GX
  • 5 — External
  • 6 — Stratix V
  • 7 — Arria V
  • 8 — Cyclone V
  • 9 — Arria 10
3 1 — Soft IP (SIP)

This ID indicates that the PCIe protocol stack is implemented in soft logic. If unspecified, the IP is considered a hard IP.

2:0 Platform Designer PCIe interface type
  • 0 — 64 bits
  • 1 — 128 bits
  • 2 — 256 bits
  • 3 — Desc/Data (that is, Avalon® -Streaming ( Avalon® -ST) interface)
  • 4 — Avalon® -MM interface
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